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Guild: wafer.space Community
Channel: 𐦂𖨆𐀪𖠋 - Friends / charz
Topic: Channel for the discussion around development of better characterization of open source process technologies such as GF180MCU.

This includes development around;
 * Physical layout of test structure designs
 * Simulation and TCAD of test structures
 * Collection of real world results from test structures
 * Understanding the PCM (process control monitoring) structures that already exist

Example details can be found @ https://bit.ly/test-open-pdk
After: 2026-10-31 11:59 p.m.
Before: 2026-12-01 12:00 a.m.
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[2026-11-02 8:19 a.m.] namibj



[2026-11-02 8:19 a.m.] namibj
@Agenxy (I briefly thought an RC approximation of a Bias Tee could allow measuring capacitance with a tiny inverter DC-shielded through a MIM cap from the DUT node and it's VDD current measured across a range of frequencies and supply voltages and with an unloaded replica nearby that can be measured to "zero-out" the capacitance measurement. But RC lossy and lossy implies poor dynamic range.)

Any particular ideas other than just a fuzzy concept of "build ring oscillator from DUTs, siphon off oscillation, divide down, plot output frequency against supply voltage, ???, profit"?


[2026-11-02 8:38 a.m.] namibj
Junction capacitance should probably be measurable via forward current against the junction and a separate replica of it's geometry but connected to a rather dedicated junction small-signal capacitance vs. bias voltage testing circuit,

and gate capacitance is even easier because the actually-manufactured geometry is pretty restricted at the end and the gate itself is a very high impedance node and I'd expect essentially all aspects of transient standard cell behavior that are relevant to be handled with extraction adjacent geometry interference fudge factors to the extracted SPICE instance parameters which you that extend should be able to prove themselves under DC conditions.

After all, on gf180mcuD we don't get any active devices that are particularly close to the litho limits, so device geometry distortion isn't going to be that strong. The one notable part, STI-induced strain, is not limited to SCL connectivity and thus calibrating extraction models of relevant geometry effects shouldn't be _too_ hard. Low key feels like it'd be an exercise in managing `dummyCOMP`/dummy-fill-blocks to cover the entire relevant spectrum of STI induced strain intensity and in a way that'll e-test nicely...


[2026-11-02 8:38 p.m.] 0xaef
@namibj the capacitance-extraction side is outside my depth.. so I’ll defer to you on CBCM vs. inferring it from DC. For the ring oscillator one ring per key cell and drive strength, an ondie divider and counter so the slow tester just reads a frequency, measured across supply voltage and two temperatures. We'd' compare that against the Liberty timing predictions.. which iswhat we care about. I''l draft that digital block and the analysis and we'll see if that's useful


[2026-11-02 9:59 p.m.] namibj
@Tholin 's digital die might sacrifice spare area to them, with an edge propagation blocking cell as part of the ring so they won't need power gating with all the issues to supply voltage droop those entail.
That die has no analog pins for us, but might have 1~2 mm^2 of SCL area and a spare mode select pin code during which we can use _plenty_ of the digital GPIOs.


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